One of equalizer circuits which compensate for a signal loss due to intersymbol interference (ISI) occurring due to influence of a bit sequence of a received data signal is a decision feedback equalizer (DFE) circuit (refer to, for example, Patent Literatures 1, 2). The compensation in the decision feedback equalizer circuit is performed based on the decision result of the past bit sequence, and a floating-tap decision feedback equalizer circuit can compensate for the influence due to an arbitrary bit in the bit sequence.
As illustrated as an example in FIG. 7, the floating-tap decision feedback equalizer circuit includes an addition circuit 701, a comparison circuit 702, a plurality of D latch circuits 703, a selection circuit (multiplexer circuit) 704, and a digital analog (DA) conversion circuit 705. The addition circuit 701 adds a compensation signal SG1 outputted from the DA conversion circuit 705 according to a bit selected from the past bit sequence to an input data signal IDT. The comparison circuit 702 performs binary determination on the output signal of the addition circuit 701, and outputs a determination result as an output data signal ODT.
The plurality of D latch circuits 703 are driven by a not-illustrated clock signal, and are connected in cascade as illustrated in FIG. 7 to hold the output data signal ODT. FIG. 7 illustrates an example including eight D latch circuits 703-1 to 703-8 (the number of taps is 8) which can hold past 8 bits. The output data signal ODT outputted from the comparison circuit 702 is inputted into the D latch circuit 703-1, and the output signal of the D latch circuit 703-i (i=integer of 1 to 7) is inputted into the D latch circuit 703-(i+1).
The multiplexer circuit 704 receives output signals of the plurality of D latch circuits 703, and selects and outputs the output signal of the D latch circuits 703 corresponding to the selected bit. The DA conversion circuit 705 digital-to-analog converts the output signal of the multiplexer circuit 704 according to the coefficient depending on the compensation intensity to generate and output the compensation signal SG1.
The floating-tap decision feedback equalizer circuit 700 illustrated in FIG. 7 selects by the multiplexer circuit 704 the past bit sequence held in the D latch circuit 703 to thereby select the position where the compensation is performed, decides the compensation intensity by the DA conversion circuit 705, and performs feedback to the addition circuit 701. For example, in the case of compensating for the influence by the data signal 5 UIs (unit intervals) ago, the output signal of the D latch circuit (L5) 703-5 is selected by the multiplexer circuit 704 and outputted to the DA conversion circuit 705. In this manner, the floating-tap decision feedback equalizer circuit 700 reflects the influence of the past data signal to the input data signal IDT to compensate for the signal loss due to the intersymbol interference.
In the conventional floating-tap decision feedback equalizer circuit 700 illustrated in FIG. 7, the input signal into the DA conversion circuit 705 delays by a delay amount (Tcd+Tmux) obtained by totaling a delay Tcd by the D latch circuit 703 and a delay Tmux by the multiplexer circuit 704 as illustrated in FIG. 8. Therefore, if the operation speed of the circuit increases, the timing of feedback of the compensation signal SG1 to the addition circuit 701 becomes severe.
Further, the conventional floating-tap decision feedback equalizer circuit 700 illustrated in FIG. 7 can spread the compensation range by increasing the number of D latch circuits 703, but when the number of D latch circuits 703 is increased, the load on the multiplexer circuit 704 increases to make the delay Tmux larger. As a result, the timing of feedback of the compensation signal SG1 to the addition circuit 701 becomes severe.
Patent Literature 1: Japanese Laid-open Patent Publication No. 2015-192200
Patent Literature 2: Japanese Laid-open Patent Publication No. 2000-49664